The present invention generally relates to an image scanner apparatus such as a facsimile machine and a digital copier, and more particularly to an image full-scale determination apparatus in which a reference voltage to be applied to an analog-to-digital converter which converts an analog image signal supplied from an image scanner to a digital image signal, is automatically generated.
A digital image scanner is typical of devices which employ an analog-to-digital converter (hereafter simply referred to as an A/D converter).
FIG.1 illustrates an essential part of the structure of a digital image scanner. Referring to FIG.1, an optical image formed by light reflected onto a document surface is imaged onto a light receiving surface of an image sensor 1 such as a charge-coupled device, and is thereby converted to a corresponding electric analog image signal. Then, the analog image signal is subjected to an analog process implemented by a sample and hold/amplification circuit 2, and is then supplied to an A/D converter 3. The A/D converter 3 converts the analog image signal supplied from the sample and hold/amplification circuit 2 to a digital image signal.
FIG.2 schematically shows an example of the structure for the A/D converter 3. The A/D converter 3 of FIG.2 has power source terminals V.sub.DD, ground terminals V.sub.SS, a single analog input terminal V.sub.IN, a plurality of digital output terminals B1-B8 (8 bits, in this case), a clock terminal CLK to which a clock signal used for defining the operation timing of the A/D converter 3 is applied, an upper-limit setting terminal V.sub.REF+, and a lower-limit setting terminal V.sub.REF-. The upper-limit setting terminal V.sub.REF+ is used for setting the upper limit V.sub.REF+ of a reference voltage for the A/D conversion, and the lower-limit setting terminal V.sub.REF- is used for setting the lower limit V.sub.REF- of the reference voltage for the A/D conversion. Further, the illustrated A/D converter 3 is provided with an overflow terminal OFW for outputting an overflow. In the A/D converter 3, there are arranged a group of comparators 4, a latch circuit 5, an encoder 6, a flip-flop 7 and a group of tri-state buffers 8 in this order toward the output side from the input side. A clock generator 9 generates clock signals .phi..sub.1 and .phi..sub.2. The sum total of the digital outputs Bi is based on an analog input signal V.sub.IN, the reference voltage upper-limit V.sub.REF+ and the reference voltage lower-limit V.sub.REF-. When the full scale of the digital output is represented as FS, the total sum of the digital outputs Bi is expressed as follows: EQU Bi=[(V.sub.IN -V.sub.REF-)/(V.sub.REF+ -V.sub.REF-)].multidot.FS
When the digital output has a resolution corresponding to 8 bits (i=8), and the lower-limit setting terminal V.sub.REF- is set to ground potential, the above-indicated formula is rewritten as follows: EQU Bi=(V.sub.IN /V.sub.REF+).multidot.255
It can be seen from the above formula that the total sum of the digital outputs Bi is based on the ratio of the input voltage to the reference voltage upper-limit V.sub.REF+.
A problem arises in setting the reference voltage upper-limit V.sub.REF+. When the reference voltage upper-limit V.sub.REF+ is lower than the input voltage V.sub.IN, the digital output is 255 of the full scale. On the other hand, when the reference voltage upper-limit V.sub.REF+ is much higher than the input voltage V.sub.IN, this is wasteful of gradation. Therefore, it is desired that the reference voltage upper-limit V.sub.REF+ is set equal to a possible maximum level of the input voltage V.sub.IN.
A description is given of a conventional configuration of an image data processing circuit including the sample and hold/amplification circuit 2 and A/D converter 3 shown in FIG.1, with reference to FIG.3. Referring to this figure, a charge-coupled device (hereafter simply referred to as a CCD) 11 is supplied with a timing pulse for data transfer and shifting. The CCD 11 generates an image signal OS and a dark signal DOS by self-scan of the CCD 11. The generated image signal OS and dark signal DOS are supplied to a buffer circuit 12, which amplifies the difference between the signals. Thereby, noise such as CCD reset noise is eliminated from the image signal OS. The output signal of the differential amplifier 12 is a pulse-like signal, and includes a direct current offset (hereafter simply referred to as a DC offset. The DC offset is removed as follows. First, a switch 13 is closed in response to a zero clock ZCLK, so that zero clamping is done. The zero clamping is carried out in order to determine zero level of the image signal output from the buffer circuit 12. Generally, the zero clamping is done by turning the switch 13 ON with a timing immediately after applying the reset pulse to the CCD 11. Secondly, a sample and hold operation is carried out by using a switch 14 and a capacitor Cs. That is, the switch 14 is turned ON to charge up the capacitor Cs only with a timing when the output of the CCD 11 correctly indicates image levels proportional to the rate of reflection on the document. The charge voltage across the capacitor Cs is applied to a buffer of a field effect transistor (hereafter simply referred to an FET) 15. Then, the FET 15 outputs, as a source output, an analog image signal which is generated based on a reference of zero volt.
The image signal output from the FET 15 is level-changed to a predetermined voltage Vo by an operational amplifier 16, and is then supplied to an reference voltage terminal REF of a digital-to-analog converter (hereafter simply referred to as a D/A converter) 17. On the other hand, a digital input terminal of the D/A converter 17 is supplied with shading correction data SDATA, which will be described later. An output signal V.sub.DA of the D/A converter 17 is proportional to a value obtained by multiplying the digital signal at the digital input terminal by the shading correction data SDATA, and is represented as follows: EQU V.sub.DA .alpha.Vo.times.SDATA
The output signal V.sub.DA of the D/A converter 17 is supplied directly to an operational amplifier 19, and on the other hand, to the operational amplifier 19 through a switch 18. The operational amplifier 19 samples and holds a dummy signal DS, which is turned ON with a timing relating to a dummy pixel provided in the CCD 11. The above dummy pixel is a pixel which is located outside an effective pixel arrangement and which is held in a light interrupting state. Therefore, the dummy pixel always generates a dark signal component. Then, the operational amplifier 19 subtracts the dark signal component from the image signal V.sub.DA. Thereby, the operational amplifier 19 generates a real analog image signal V.sub.IN in which the dark current component is already eliminated. The analog image signal V.sub.IN is an input image signal to be supplied to an A/D converter 20.
On the other hand, a switch 21 is supplied with a white reference signal WS, which is generated with a timing when the CCD 11 scans a white reference plate 25 (FIG.4). During the time when the switch 21 is ON, two operational amplifiers 22 and 23 connected in series, are connected between the output of the operational amplifier 19 and the reference voltage terminal REF of the A/D converter 20. During the time when the CCD 11 scans the white reference plate 25, the analog image signal V.sub.IN output from the operational amplifier 19 is a white reference output. The white reference output is sampled and held with the timing of the white reference signal WS by which the switch 21 is turned ON. The sampled and held signal is then subjected to a level adjustment with the operational amplifier 22 and a variable resistor VR. A voltage signal of an adjusted level supplied from the variable resistor VR is a reference voltage V.sub.REF used for determining the full scale of the image signal.
FIG.4 also illustrates a contact glass 26, an image focusing lens 27, and a lamp 28 for exposure. A reference 1 indicates the effective image range.
An image clock VCLK is applied to the A/D converter 20, which converts the analog image signal V.sub.IN in synchronism with the image clock VCLK. In the A/D converter 20, the reference voltage V.sub.REF for A/D conversion is used as the reference (full scale). For example, when the analog image signal V.sub.IN consists of 8 bits, the output signal of the the A/D converter 20 is (V.sub.IN /V.sub.REF).multidot.255. In this way, the analog image signal V.sub.IN is converted to a corresponding digital image signal by the A/D converter 20. Then, the digital image signal thus generated is subjected to a data conversion by a real only memory (hereafter simply referred to as a ROM) 14, which generates a corresponding digital video data VDATA in response to a timing signal FSHD.
However, the above-mentioned reference voltage determination process with the structure of FIG.3 has the following disadvantages. An analog circuit which is made up of the operational amplifiers 22, 23, and the variable resistor VR affects the stability of the system (circuit), even when the analog circuit is constructed by high-speed parts. Additionally, since the manual adjustment with the variable resistor VR is employed, variations in characteristics may occur over image data processing circuits. Further, the image angle of the CCD 11 is extended over the effective image range. Therefore, a decreased number of pixels is permitted to be arranged in the effective image range, and therefore the effective scan rate of the CCD 11 is decreased.
A further description is given of the above-indicated disadvantages. In analog configurations, noise is one of the reasons which cause the system to be unstable. For example, when noise, particularly pulse like noise having a fixed period, is introduced into a power source, the noise suppression effect of amplifiers is extremely deteriorated. As a result, noise is also introduced into the data VDATA of the system. The reference voltage for the A/D converter 20 which is generated under the above-mentioned unstable condition, is not reliable. Further, a fluctuation of signal level may occur due to temperature variation. Therefore, time deterioration in image quality may occur for long use. On the other hand, the level variation may occur even in the variable resistor VR, with which the manual adjustment is done. Therefore, variations in characteristics over circuits are great.
Shading correction is further described. Generally, shading correction is employed for image scanners for optically reading documents. This results from illuminance distribution characteristics of a light source, focusing characteristics of lenses, and sensitivity fluctuation over pixels of CCDs. The illuminance distribution characteristics exhibit that an illuminance obtained at the center of the light source is larger than that obtained at both the sides thereof. The focusing characteristics exhibit that light is converged to a center portion of a lens. This is so-called cosine-power-of-4-rule. Generally, the maximum sensitivity variation is .+-. 10%.
FIG.5A illustrates a waveform of a signal which is obtained by reading an image of uniform white and amounts to one line in a main scanning direction. As is illustrated, signal levels at a center portion of the line are higher than those in other portions, and fluctuate with a short period (pixel period). When the signal of FIG.5A is subjected to the shading correction, the resultant signal waveform of FIG.5B is obtained. As is illustrated in FIG.5B, the resultant signal waveform is almost uniform over the line. In FIGS.5A and 5B, broken lines represent the corresponding reference voltage upper-level V.sub.REF+.
A variety of shading correction has been proposed. One of the effective proposals is described below. A white reference plate is placed in an image effective range 1 of the CCD 11. The above white reference plate is different from the white reference plate 25 shown in FIG.4. Before the normal image reading, the white reference plate is scanned, and thereby a signal waveform as shown in FIG.5A is obtained. Next, as shown in FIG.6A, the A/D conversion is carried out by an A/D converter 29 (of the same structure as the A/D converter 3) through a path indicated by broken lines. The obtained digital image data is stored in a random access memory (hereafter simply referred to as a RAM) 30. Then, during normal reading operation, the digital image data is derived from the A/D converter 20 through a path including a shading correction circuit 31 indicated with solid lines. The shading correction circuit 31 includes a digital-to-analog multiplier and a ROM. Variations in sensitivity can be corrected by dividing the image signal applied to the shading correction circuit 31 by the digitized white signal stored in the RAM 30.
Anyhow, it is necessary to use two different reference voltages V.sub.REF1 and V.sub.REF2 (FIGS.6A and 6B) for the A/D conversion performed at the time of shading correction and normal image reading. Conventionally, two reference voltages V.sub.REF1 and V.sub.REF2 are generated with a circuit shown in FIG.6B. Referring to this figure, two analog switches 32 and 33 are used. The analog switch 32 is turned ON only during the shading correction, and on the other hand, the analog switch 33 is turned ON during the normal reading operation. When the shading correction data is generated by reading the white reference plate, the reference voltage V.sub.REF1 to be supplied to a terminal V.sub.REF+ of an A/D converter is adjusted by tuning the variable resistor VR1 so as to become equal to the maximum value of the analog image signal V.sub.IN while observing the output waveform on an oscilloscope. In the normal reading operation, the reference voltage V.sub.REF2 to be supplied to the terminal V.sub.REF+ of the A/D converter 29 is adjusted by tuning the variable resistor VR2 so as to become equal to the maximum value of the analog image signal V.sub.IN.
However, the above adjustment has the following disadvantages. First, it is necessary to manually adjust the variable resistors VR1 and VR2, which is troublesome and needs long time. Additionally, since the adjustment is manually done while observing the oscilloscope, it is impossible to set the reference voltages to the maximum level of the input image signal V.sub.IN with high precision. Moreover, an amount of light emitted by the light source is fluctuated due to variations in the power source voltage, rise response characteristics exhibited when turning ON the power source, and time deterioration of the light source. For these reasons, the level of the analog image signal V.sub.IN varies. Once the adjustment is completed, an error may occur in a few minutes.